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complementary outputs connected to the respective low-side transistors (UL, VL, WL shown in
Figure 19.21 (p. 256) ). Transistors used in such a bridge often do not open/close instantaneously, and
using the exact complementary inputs for the high and low side of a half-bridge may result in situations
where both gates are open. This can give unnecessary current-draw and short circuit the power supply.
The DTI unit provides dead-time insertion to deal with this problem.
Figure 19.21. TIMER Triple Half-Bridge
UH
UL
VH
VL
WH
WL
W
V
U
For each of the 3 compare-match outputs of TIMER0, an additional complementary output is provided by
the DTI unit. These outputs, named TIM0_CDTI0, TIM0_CDTI1 and TIM0_CDTI2 are provided to make
control of e.g. 3-channel BLDC or PMAC motors possible using only a single timer, see Figure 19.22 (p.
256) .
Figure 19.22. TIMER Overview of Dead-Time Insertion Block for a Single PWM channel
Original PWM (TIM0_CCx_pre)
DTFALLT
Select
DTRISET
HFPERCLK TIMERn
Clock control
Counter
=0
Prim ary output (TIM0_CCx)
Com plem entary Output (TIM0_CDTIx)
The DTI unit is enabled by setting DTEN in TIMER0_DTCTRL. In addition to providing the
complementary outputs, the DTI unit then also overrides the compare match outputs from the timer.
The DTI unit gives the rising edges of the PWM outputs and the rising edges of the complementary
PWM outputs a configurable time delay. By doing this, the DTI unit introduces a dead-time where both
the primary and complementary outputs in a pair are inactive as seen in Figure 19.23 (p. 256) .
Figure 19.23. TIMER Polarity of Both Signals are Set as Active-High
Original PWM
dt1
TIM0_CC0
dt2
TIM0_CDTI0
2011-04-12 - d0001_Rev1.10
256
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